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Additional tests - #185

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ElioPalleschi wants to merge 8 commits into
pulp-platform:mainfrom
FondazioneChipsIT:epalleschi/vfu_and_vlsu_additions
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ElioPalleschi wants to merge 8 commits into
pulp-platform:mainfrom
FondazioneChipsIT:epalleschi/vfu_and_vlsu_additions

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This pull request introduces support for register load/store instructions with the related tests, and additional tests for other instructions.

This PR is related to this vpu.

Hardware support for new vector instructions

Added support for whole register group load instructions (VL1RE8/16/32/64, VL2RE8/16/32/64, VL4RE8/16/32/64, VL8RE8/16/32/64) and corresponding store instructions (VS1R, VS2R, VS4R, VS8R) in the main Snitch core module (snitch.sv).

Added tests
Added tests for vfredosum, vmv, vadc, vmadc, vsbc, vmsbc, vlre and vsr.

@ElioPalleschi
ElioPalleschi marked this pull request as ready for review October 29, 2026 09:51
Copilot AI balanced review requested due to automatic review settings October 29, 2026 09:51

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rgiunti
rgiunti previously approved these changes Oct 29, 2026

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LGTM. @Navaneeth-KunhiPurayil could you start the CI for this PR? Thanks

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3 participants