Additional tests

Bender.lock

@@ -133,7 +133,7 @@ packages:
     - riscv-dbg
     - tech_cells_generic
   spatz_vpu:
-    revision: 39dc0e37275191144e3158039625a0d22f90abd2
+    revision: f489b7f9e296e41134104fbab822482a22e94a43
     version: null
     source:
       Git: https://github.com/pulp-platform/spatz_vpu.git

hw/ip/snitch/src/snitch.sv

@@ -2794,7 +2794,23 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VLUXEI8_V,
       riscv_instr::VLUXEI16_V,
       riscv_instr::VLUXEI32_V,
-      riscv_instr::VLUXEI64_V: begin
+      riscv_instr::VLUXEI64_V,
+      riscv_instr::VL1RE8_V,
+      riscv_instr::VL1RE16_V,
+      riscv_instr::VL1RE32_V,
+      riscv_instr::VL1RE64_V,
+      riscv_instr::VL2RE8_V,
+      riscv_instr::VL2RE16_V,
+      riscv_instr::VL2RE32_V,
+      riscv_instr::VL2RE64_V,
+      riscv_instr::VL4RE8_V,
+      riscv_instr::VL4RE16_V,
+      riscv_instr::VL4RE32_V,
+      riscv_instr::VL4RE64_V,
+      riscv_instr::VL8RE8_V,
+      riscv_instr::VL8RE16_V,
+      riscv_instr::VL8RE32_V,
+      riscv_instr::VL8RE64_V: begin
         if (RVV) begin
           write_rd        = 1'b0;
           uses_rd         = 1'b0;
@@ -2841,7 +2857,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
       riscv_instr::VSUXEI8_V,
       riscv_instr::VSUXEI16_V,
       riscv_instr::VSUXEI32_V,
-      riscv_instr::VSUXEI64_V: begin
+      riscv_instr::VSUXEI64_V,
+      riscv_instr::VS1R_V,
+      riscv_instr::VS2R_V,
+      riscv_instr::VS4R_V,
+      riscv_instr::VS8R_V: begin
         if (RVV) begin
           write_rd        = 1'b0;
           uses_rd         = 1'b0;

sw/riscvTests/CMakeLists.txt

@@ -46,6 +46,10 @@ add_snitch_test(vsetvli isa/rv64uv/vsetvli.c)
 add_snitch_test(vsetivli isa/rv64uv/vsetivli.c)
 add_snitch_test(vsetvl isa/rv64uv/vsetvl.c)
 
+add_snitch_test(vadc  isa/rv64uv/vadc.c)
+add_snitch_test(vmadc isa/rv64uv/vmadc.c)
+add_snitch_test(vsbc  isa/rv64uv/vsbc.c)
+add_snitch_test(vmsbc isa/rv64uv/vmsbc.c)
 add_snitch_test(vadd  isa/rv64uv/vadd.c)
 add_snitch_test(vsub  isa/rv64uv/vsub.c)
 add_snitch_test(vrsub isa/rv64uv/vrsub.c)
@@ -197,11 +201,13 @@ add_snitch_test(vle8 isa/rv64uv/vle8.c)
 add_snitch_test(vle16 isa/rv64uv/vle16.c)
 add_snitch_test(vle32 isa/rv64uv/vle32.c)
 add_snitch_test(vle64 isa/rv64uv/vle64.c)
+add_snitch_test(vlre isa/rv64uv/vlre.c)
 add_snitch_test(vse8 isa/rv64uv/vse8.c)
 add_snitch_test(vse16 isa/rv64uv/vse16.c)
 add_snitch_test(vse32 isa/rv64uv/vse32.c)
 add_snitch_test(vse64 isa/rv64uv/vse64.c)
 add_snitch_test(vss isa/rv64uv/vss.c)
+add_snitch_test(vsr isa/rv64uv/vsr.c)
 
 add_snitch_test(vill isa/rv64uv/vill.c)
 set_property(TEST ${SNITCH_TEST_PREFIX}rtl-vill PROPERTY WILL_FAIL TRUE)

sw/riscvTests/isa/rv64uv/vadc.c

@@ -0,0 +1,212 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Generated test for vadc.vim (Vector Add with Carry, immediate format)
+
+#include "vector_macros.h"
+
+// vadc.vim with carry-in = 0 for all elements
+void TEST_CASE1(void) {
+  VSET(16, e8, m8);
+  VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00); // Carry-in is 0
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U8(1, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e16, m8);
+  VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U16(2, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e32, m8);
+  VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U32(3, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+#if ELEN == 64
+  VSET(16, e64, m8);
+  VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U64(4, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+#endif
+}
+
+// vadc.vim with carry-in = 1 for all elements
+void TEST_CASE2(void) {
+  VSET(16, e8, m8);
+  VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xFF, 0xFF); // Carry-in is 1
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U8(5, v24, 7, 8, 9, 10, 11, 12, 13, 14, 7, 8, 9, 10, 11, 12, 13, 14);
+
+  VSET(16, e16, m8);
+  VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U16(6, v24, 7, 8, 9, 10, 11, 12, 13, 14, 7, 8, 9, 10, 11, 12, 13, 14);
+
+  VSET(16, e32, m8);
+  VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U32(7, v24, 7, 8, 9, 10, 11, 12, 13, 14, 7, 8, 9, 10, 11, 12, 13, 14);
+
+#if ELEN == 64
+  VSET(16, e64, m8);
+  VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U64(8, v24, 7, 8, 9, 10, 11, 12, 13, 14, 7, 8, 9, 10, 11, 12, 13, 14);
+#endif
+}
+
+// This will add (imm=5) + 0 to even indices, and (imm=5) + 1 to odd indices.
+void TEST_CASE3(void) {
+  VSET(16, e8, m8);
+  VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  // Index: 0 (+5), 1 (+6), 2 (+5), 3 (+6)...
+  VCMP_U8(9, v24, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e16, m8);
+  VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U16(10, v24, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e32, m8);
+  VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U32(11, v24, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+#if ELEN == 64
+  VSET(16, e64, m8);
+  VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  VCMP_U64(12, v24, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+#endif
+}
+
+// Testing immediate values around boundaries, where carry makes it overflow
+void TEST_CASE4(void) {
+  VSET(16, e8, m8);
+  // -2 (0xFE), -1 (0xFF), 0, etc.
+  VLOAD_8(v8, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250, 250);
+  VLOAD_8(v0, 0xAA, 0xAA); // 10101010
+  VCLEAR(v24);
+  asm volatile("vadc.vim v24, v8, 5, v0");
+  // Even elements: 250 + 5 + 0 = 255
+  // Odd elements: 250 + 5 + 1 = 256 (rolls over to 0 for 8-bit)
+  VCMP_U8(13, v24, 255, 0, 255, 0, 255, 0, 255, 0, 255, 0, 255, 0, 255, 0, 255, 0);
+
+  // Note: Only included e8 here to keep it concise, but the pattern mimics the other cases.
+}
+
+void TEST_CASE5(void) {
+  // 1. Carry-in = 0 (v0 = 0x00)
+  VSET(16, e8, m8);
+  VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v16, 10, 20, 30, 40, 50, 60, 70, 80, 10, 20, 30, 40, 50, 60, 70, 80);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vvm v24, v8, v16, v0");
+  VCMP_U8(14, v24, 11, 22, 33, 44, 55, 66, 77, 88, 11, 22, 33, 44, 55, 66, 77, 88);
+
+  VSET(16, e16, m8);
+  VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v16, 10, 20, 30, 40, 50, 60, 70, 80, 10, 20, 30, 40, 50, 60, 70, 80);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vvm v24, v8, v16, v0");
+  VCMP_U16(15, v24, 11, 22, 33, 44, 55, 66, 77, 88, 11, 22, 33, 44, 55, 66, 77, 88);
+
+  // 2. Carry-in = 1 (v0 = 0xFF)
+  VSET(16, e32, m8);
+  VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v16, 10, 20, 30, 40, 50, 60, 70, 80, 10, 20, 30, 40, 50, 60, 70, 80);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  VCLEAR(v24);
+  asm volatile("vadc.vvm v24, v8, v16, v0");
+  VCMP_U32(16, v24, 12, 23, 34, 45, 56, 67, 78, 89, 12, 23, 34, 45, 56, 67, 78, 89);
+
+#if ELEN == 64
+  // 3. Alternating Carry-in (v0 = 0xAA -> Even gets +0, Odd gets +1)
+  VSET(16, e64, m8);
+  VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v16, 10, 20, 30, 40, 50, 60, 70, 80, 10, 20, 30, 40, 50, 60, 70, 80);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vvm v24, v8, v16, v0");
+  VCMP_U64(17, v24, 11, 23, 33, 45, 55, 67, 77, 89, 11, 23, 33, 45, 55, 67, 77, 89);
+#endif
+}
+
+void TEST_CASE6(void) {
+  const uint32_t scalar = 5;
+
+  // 1. Carry-in = 0 (v0 = 0x00)
+  VSET(16, e8, m8);
+  VLOAD_8(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vxm v24, v8, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U8(18, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e16, m8);
+  VLOAD_16(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0x00, 0x00);
+  VCLEAR(v24);
+  asm volatile("vadc.vxm v24, v8, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U16(19, v24, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  // 2. Carry-in = 1 (v0 = 0xFF)
+  VSET(16, e32, m8);
+  VLOAD_32(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  VCLEAR(v24);
+  asm volatile("vadc.vxm v24, v8, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U32(20, v24, 7, 8, 9, 10, 11, 12, 13, 14, 7, 8, 9, 10, 11, 12, 13, 14);
+
+#if ELEN == 64
+  // 3. Alternating Carry-in (v0 = 0xAA -> Even gets +0, Odd gets +1)
+  VSET(16, e64, m8);
+  VLOAD_64(v8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v24);
+  asm volatile("vadc.vxm v24, v8, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U64(21, v24, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+#endif
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}