[ElioPalleschi]

This pull request introduces support for the vl<nf>re<eew>.v and vs<nf>r.v instructions and fixes to vfredosum.v, vmv.x.s, vadc.v, vmadc.v, vsbc.v and vmsbc.v. After the synthesis, the new vpu module's area has increased by 0.5%.

These changes are verified by the tests introduced by this PR.

Support for vl<nf>re<eew>.v and vs<nf>r.v

Added decoding, control, and execution support for the VLRE (VL1RE8_V, VL2RE8_V, etc.) and VSR (VS1R_V, VS2R_V, etc.) instructions. They are handled by converting them into equivalent flat, unmasked, unit-stride byte transfers.

vfredosum.v fix

Before this change, vfredosum was executed as a parallel tree, like vfredusum.

• The ordered path replaces the tree with a sequential chain on FPU 0. Each active element is added to a running accumulator, and the next add waits for the previous result.
• The existing flow is unchanged for vfredusum, but for ordered reductions, the FSM transitions to a new set of states.

vmv.x.s fix

Originally, the VFU simply copied the entire lower word of a vector register into the scalar register without extracting element 0 or sign-extending it to XLEN according to the active element width.

• Introduced a new bit is_int_scalar_move to the op_arith struct to differentiate it from other scalar-producing operations, and set it to 1 for vmv.x.s.
• Passed the active element width from the vector type CSR.
• Changed the scalar_result assignment to adapt it for vmv.x.s.

vadc.v, vmadc.v, vsbc.v, vmsbc.v fix

These instructions didn't use the carry-in, and instead treated v0 as a write mask.

• Added support for the carry-in by correctly fetching and slicing v0 for these instructions.
• Fixed the routing for 16-bit and 32-bit carry-in.

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[rgiunti]

Thanks @ElioPalleschi, it looks good to me.