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Core2: reset the LCD through the AXP2101 bit on the new PMIC - #354
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Panel_M5StackCore2_T::rst_control always toggled AXP192 reg 0x96 bit1 (GPIO4 = LCD RST). On the AXP2101 (Core2 v1.1 and later) reg 0x96 is the BLDO1 voltage, which powers the backlight, so every panel init nudged the backlight voltage and never reset the LCD. The panel now carries the reset register, set at construction from the detected PMIC: 0x90 bit1 (ALDO2 enable) on the AXP2101, the same bit the detector already uses.
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What changes
On Core2 boards with the AXP2101 PMIC (v1.1), the panel's
rst_control()toggled reg 0x96 bit1. That is the LCD reset line (GPIO4) on the AXP192, but on the AXP2101 reg 0x96 is the BLDO1 voltage, which powers the backlight. Every panel init therefore nudged the backlight voltage and never reset the LCD.The panel now carries its reset register, chosen at construction from the detected PMIC: reg 0x90 bit1 (ALDO2 enable) on the AXP2101, the same bit the board detection already uses for this reset, and reg 0x96 bit1 on the AXP192 as before.
Checked
getPanel()->init(true), then read the display power mode (0x0A). Init does not send NORON, so the normal-mode state only comes back through a hardware reset.init(false)is the control.