cstool

Workflow runs for cstool

• x86: fix RETF register access and groups

  completed successfully:
  cstool#408:Pull request#3153openedbyraaller
  raaller:fix/x86-retf-registers-2822

  Nov 5, 20268m 43s
  More actions for workflow run 408

• x86: decode reserved x87 register aliases (#3141)

  completed successfully:
  cstool#407:Commit04fd70bpushedbyRot127
  next

  Nov 4, 20267m 2s
  More actions for workflow run 407

• x86: decode reserved x87 register aliases

  completed successfully:
  cstool#406:Pull request#3141synchronizebyraaller
  raaller:fix/x86-x87-reserved-aliases-3117

  Nov 3, 20267m 36s
  More actions for workflow run 406

• build(deps): bump pypa/cibuildwheel from 4.3.4 to 4.3.5

  completed successfully:
  cstool#405:Pull request#3152openedbydependabot[bot]Bot
  dependabot/github_actions/pypa/cibuildwheel-4.3.5

  Nov 3, 202623m 29s
  More actions for workflow run 405

• build(deps): bump pypa/cibuildwheel from 4.3.4 to 4.3.5

  completed successfully:
  cstool#404:Commit59bf96epushedbydependabot[bot]Bot
  dependabot/github_actions/pypa/cibuildwheel-4.3.5

  Nov 3, 202622m 26s
  More actions for workflow run 404

• x86: add missing FPU group for FCMOVNB (#3149)

  completed successfully:
  cstool#403:Commite4e3cfbpushedbyRot127
  next

  Nov 2, 20266m 25s
  More actions for workflow run 403

• build(deps): bump pypa/cibuildwheel from 4.3.1 to 4.3.4 (#3144)

  completed successfully:
  cstool#402:Commitae90272pushedbyRot127
  next

  Nov 2, 20269m 57s
  More actions for workflow run 402

• [finding - write your own PR title] loongarch: vstelm/xvstelm detail uses the offset immediate as the memory base register

  completed successfully:
  cstool#401:Pull request#3150openedbySamin061
  Samin061:loongarch-stelm-mem-operand

  Nov 2, 20268m 21s
  More actions for workflow run 401

• x86: add missing FPU group for FCMOVNB

  completed successfully:
  cstool#400:Pull request#3149openedbyraaller
  raaller:fix/x86-fcmovnb-fpu-group-1694

  Nov 1, 20265m 22s
  More actions for workflow run 400

• x86: decode reserved x87 register aliases

  completed successfully:
  cstool#399:Pull request#3141synchronizebyraaller
  raaller:fix/x86-x87-reserved-aliases-3117

  Oct 31, 20265m 57s
  More actions for workflow run 399

• Disable debug build wheel workflow.

  completed successfully:
  cstool#398:Pull request#3148synchronizebyRot127
  Rot127:risc-v

  Oct 30, 20268m 7s
  More actions for workflow run 398

• Disable debug build wheel workflow.

  completed successfully:
  cstool#397:Pull request#3148synchronizebyRot127
  Rot127:risc-v

  Oct 30, 20264m 34s
  More actions for workflow run 397

• Disable debug build wheel workflow.

  completed successfully:
  cstool#396:Pull request#3148openedbyRot127
  Rot127:risc-v

  Oct 30, 20267m 38s
  More actions for workflow run 396

• riscv: give c.slli hint form a distinct instruction ID

  requires action with the application:
  cstool#395:Pull request#3147openedbyHenglie
  Henglie:fix/riscv-c-slli-hint-id

  Oct 30, 2026Action required
  More actions for workflow run 395

• Add type hints for python bindings

  completed successfully:
  cstool#394:Pull request#3146openedbyhistoricattle
  historicattle:type

  Oct 28, 20266m 51s
  More actions for workflow run 394

• [finding - write your own PR title] ppc: PC-relative prefixed load/store detail hits CS_OP_MEM assert in ImmZeroOperand

  completed successfully:
  cstool#393:Pull request#3145openedbySamin061
  Samin061:ppc-pcrel-immzero-detail

  Oct 27, 202613m 17s
  More actions for workflow run 393

• build(deps): bump pypa/cibuildwheel from 4.3.1 to 4.3.4

  completed successfully:
  cstool#392:Pull request#3144openedbydependabot[bot]Bot
  dependabot/github_actions/pypa/cibuildwheel-4.3.4

  Oct 27, 202635m 11s
  More actions for workflow run 392

• build(deps): bump pypa/cibuildwheel from 4.3.1 to 4.3.4

  completed successfully:
  cstool#391:Commit4427837pushedbydependabot[bot]Bot
  dependabot/github_actions/pypa/cibuildwheel-4.3.4

  Oct 27, 202633m 36s
  More actions for workflow run 391

• RISC-V: CI: Make yaml parsing faster by using the C loader if it's available and add a json path to sidestep yaml entirely and exploit json's faster parsing

  completed successfully:
  cstool#390:Pull request#3140synchronizebymoste00
  moste00:feature/speedup_qemu_riscv_ci

  Oct 25, 20267m 14s
  More actions for workflow run 390

• x86: decode reserved x87 register aliases

  completed successfully:
  cstool#389:Pull request#3141openedbyraaller
  raaller:fix/x86-x87-reserved-aliases-3117

  Oct 25, 20267m 42s
  More actions for workflow run 389

• RISC-V: CI: Make yaml parsing faster by using the C loader if it's available and add a json path to sidestep yaml entirely and exploit json's faster parsing

  completed successfully:
  cstool#388:Pull request#3140synchronizebymoste00
  moste00:feature/speedup_qemu_riscv_ci

  Oct 25, 20267m 42s
  More actions for workflow run 388

• RISC-V: CI: Make yaml parsing faster by using the C loader if it's available and add a json path to sidestep yaml entirely and exploit json's faster parsing

  completed successfully:
  cstool#387:Pull request#3140openedbymoste00
  moste00:feature/speedup_qemu_riscv_ci

  Oct 25, 20266m 38s
  More actions for workflow run 387

• x86: add SSSE3 groups for PABS instructions (#3137)

  completed successfully:
  cstool#386:Commit8b95af3pushedbyRot127
  next

  Oct 24, 20265m 13s
  More actions for workflow run 386

• Update treesitter to 0.26.0 (#3138)

  completed successfully:
  cstool#385:Commitd7fd198pushedbyRot127
  next

  Oct 24, 202623m 58s
  More actions for workflow run 385

• x86: add SSSE3 groups for PABS instructions

  completed successfully:
  cstool#384:Pull request#3137synchronizebyRot127
  raaller:fix/x86-pabs-ssse3-2539

  Oct 24, 202635m 54s
  More actions for workflow run 384